A technical knowledge portal by eVision Systems GmbH

FPGA / ASIC / HDL ENGINEERING

Better HDL code.
Reliable
verification.

Practical knowledge, tools and advice for FPGA and ASIC development — with solutions from Aldec and Sigasi.

For engineers and technical decision-makers.
Illustration of an FPGA board with signal connections.

FROM PROBLEM TO SOLUTION

Where does your project stand?

Explore all topics ↗
01 / CODE

Keep complex HDL code
under control.

Understand dependencies, navigate with confidence and find errors as you write.

HDL & code quality ↗
02 / SIMULATE

Understand failures.
Debug with a purpose.

Connect your testbench, simulator and waveforms in a reproducible workflow.

Simulation & debugging ↗
03 / VERIFY

Test beyond
the normal case.

Align assertions, coverage and structured tests with your requirements.

Verification ↗
04 / AUTOMATE

Make good results
repeatable.

Structure your project and regression so the entire team benefits.

Automated workflows ↗

TOOLS WORKING TOGETHER

A traceable path
from editor to test result.

Understand the workflow ↗
01 →

Develop

Understand source code and project structure.
Sigasi Visual HDL

02 →

Check statically

Check rules and structural risks.
ALINT-PRO

03 →

Simulate

Execute and investigate behaviour.
Active-HDL / Riviera-PRO

04 ↺

Repeat

Automate tests and retain results
so the team can understand and reproduce them.

Your project determines the selection. A shared workflow does not imply universal integration of all tools; compilation and simulation are separate steps.

Illustration of an engineering workspace for simulation and verification.

FROM CODE TO INSIGHT

Understand the technology. Make informed decisions.

A useful development workflow connects tools with clear questions: what needs to be checked, how can a failure be reproduced, and which next test will move the project forward?

Explore the development workflow →

KNOWLEDGE THAT MOVES YOU FORWARD

From understanding to application.

Explore the knowledge section ↗
APPLICATION NOTES

Small examples.
Clear checks.
Explicit limitations.

Setup, testbenches and regression: our application notes describe prerequisites, original examples, expected results and the actual test status.

Explore the guides ↗

TWO PERSPECTIVES ON YOUR FLOW

Combine tools deliberately.
Make technically informed decisions.

Aldec

Simulation, debugging and static verification for FPGA and ASIC projects.

Understand Aldec’s role ↗

Sigasi

HDL development and project understanding in Visual Studio Code — with Sigasi Visual HDL.

Understand Sigasi’s role ↗

What next step would help your team?

Describe your development goal, tool environment and bottleneck. eVision Systems helps assess your needs and clarify suitable products, evaluation options and quotations.

Discuss your project ↗

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Practical knowledge about HDL, simulation and verification. New articles, application notes and insights into useful tools.